Lead Characterization Engineer

Our client is an American-based MNC from the semiconductor industry. Currently looking for Lead Engineer responsible for post-silicon and characterization activities.

JOB DESCRIPTION

• Define and own comprehensive silicon validation strategy spanning functional, electrical,
  reliability, and full system-level testing across multiple IP domains.
• Plan and execute structured validation coverage across full PVT matrices (SS/TT/FF,
  voltage, temperature) with disciplined margin tracking, guardband definition, and
  quantified risk assessment aligned to product specifications.
• Lead high-speed PHY bring-up and characterization (32Gbps+), including link training,
  tuning, and electrical margin assessment across operating corners.
• Define and execute advanced RX validation including BER bathtub analysis, JTOL
  characterization, CDR tolerance testing, stress/run-length validation, and equalization
  optimization.
• Conduct TX jitter measurement, decomposition, and root cause analysis to ensure robust
  transmitter performance and compliance readiness.
• Drive compliance preparation and certification readiness for PCI Express, DisplayPort,
  Ethernet, and HDMI.
• Lead core fabric validation including clock domain crossing stress testing, throughput
  benchmarking, and multi-IP (BRAM, DSP, accelerators) integration validation under
  worst-case conditions.
• Drive DDR, MIPI D-PHY, LVDS, and general IO validation covering protocol timing
  compliance, electrical margin analysis, skew management, and board-level signal
  integrity interactions.
• Validate PLL and clocking architectures including lock behavior, jitter performance,
  spread-spectrum clocking (SSC), dynamic frequency scaling, and measurement-tosimulation correlation.
• Lead complex cross-domain silicon debug across analog, digital, PHY, and system
  boundaries; drive structured root cause analysis and corrective action plans.
• Perform statistical margin analysis (Cpk evaluation, yield extrapolation, guardband
  optimization), prepare silicon readiness assessments, and present technical risk
  evaluations to executive leadership and customers.
• Architect scalable lab automation frameworks (Python-based automation, data
  acquisition, traceability systems), mentor engineers, standardize validation
  methodologies, and provide technical support to customers, FAEs, and internal
  stakeholders.